发明名称 METHOD FOR DETERMINING WIRING PATHWAY OF WIRING BOARD AND METHOD FOR DETERMINING WIRING PATHWAY OF SEMICONDUCTOR DEVICE
摘要 In an embodiment of the invention, a wiring pathway determining method includes: tracing continuously a first wiring forming grid to extend an additional wiring line from a starting point to one first already-selected intersection selected from plural first intersections; computing a first via allocatable region where an additional via can be allocated on a first wiring layer and a second via allocatable region where the additional via can be allocated on a second wiring layer based on positions of an already-designed wiring line and an already-designed via; allocating the additional via, in which a first already-selected intersection is included in an arbitrary position in a region of a lower surface, such that the lower surface is included in the first via allocatable region and such that an upper surface is included in a second via allocatable region; and tracing continuously a second wiring forming grid to extend the additional wiring line from the additional via to an ending point.
申请公布号 US2012060366(A1) 申请公布日期 2012.03.15
申请号 US201113029972 申请日期 2011.02.17
申请人 NAKANO MIKIO;KABUSHIKI KAISHA TOSHIBA 发明人 NAKANO MIKIO
分类号 H05K3/02;H05K3/10 主分类号 H05K3/02
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