发明名称 |
Method for Node Addition and Removal of a Circuit |
摘要 |
The present invention discloses a method for node addition and removal of a circuit. The steps of the method include: (a) providing a circuit with a plurality of nodes; (b) selecting a target node for computing mandatory assignments (MAs) of stuck-at 0 and stuck-at 1 fault tests on the target node, respectively, by a processing unit; (c) finding an added substitute node by utilizing the MAs of stuck-at 0 and stuck-at 1 fault tests of the target node by the processing unit; and (d) replacing the target node by using the added substitute node closest to primary inputs; and (e) the steps (b)˜(d) are repeated for removing the replaceable nodes and simplifying the circuit. |
申请公布号 |
US2012066542(A1) |
申请公布日期 |
2012.03.15 |
申请号 |
US20100880474 |
申请日期 |
2010.09.13 |
申请人 |
CHEN YUNG-CHIH;WANG CHUN-YAO;NATIONAL TSING HUA UNIVERSITY |
发明人 |
CHEN YUNG-CHIH;WANG CHUN-YAO |
分类号 |
G06F11/20 |
主分类号 |
G06F11/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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