发明名称 DIGITAL FREQUENCY LOCKED DELAY LINE
摘要 A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.
申请公布号 US2012063551(A1) 申请公布日期 2012.03.15
申请号 US201113299085 申请日期 2011.11.17
申请人 SCHNARR CURT 发明人 SCHNARR CURT
分类号 H04L27/06 主分类号 H04L27/06
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