| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a divider circuit preventing oscillation of a frequency divider. <P>SOLUTION: A divider circuit 1 for preventing oscillation of a frequency divider comprises: a frequency divider 20 that divides a clock signal Vc with a predetermined division ratio; a peak detector 30 that detects a peak voltage Vcp of the clock signal and holds the peak value; a reference voltage generator 40 that outputs a reference voltage Vref corresponding to a clock signal amplitude vp necessary for normal operation of the frequency divider; and a comparator 50 that compares the peak value detected by the peak detector with the reference voltage. The divider circuit includes a control terminal for inputting a control signal that indicates the start of dividing to the frequency divider. When an output signal Ve of the comparator is connected to the control terminal and the peak value exceeds the reference voltage, the comparator outputs the control signal that indicates the start of dividing to the control terminal of the frequency divider. <P>COPYRIGHT: (C)2012,JPO&INPIT |
