Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices

摘要

A system includes a system controller (102) and a configuration of series-connected semiconductor devices (104). Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer (110) for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller further includes a detector (506) for processing the first and second clock signals (S TCK ,S RCK ) to detect a phase difference therebetween; and a synchronization controller (508) for commanding an adjustment to the clock synchronizer in at least one of the devices based on the phase difference (S DIFF ) detected by the detector.