发明名称 Data transfer clock recovery for legacy systems
摘要 The present disclosure provides methods and apparatus for adapting a relatively high data rate second order SERDES receiver to receive relatively low data rate serial data, the receiver having a jog realignment by and having means for receiving the serial data as a plurality of repeated bits at the high data rate; framing the data as frames of repeated bits of the same value; examining the bits of the frame for the presence of bits which are not of the same value; upon detecting such a presence that is indicative of a framing error jogging the SERDES receiver for frame realignment; and supplying to an output of the SERDES receiver one of the bits of said same value from each frame at the low data rate.
申请公布号 GB201201580(D0) 申请公布日期 2012.03.14
申请号 GB20120001580 申请日期 2012.01.31
申请人 TEXAS INSTRUMENTS LIMITED 发明人
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