Analog-to-digital converter having a single set of comparators for a multi-stage sampling circuit and method therefor

摘要

An analog to digital converter (20) includes a first sample circuit (52) that samples an analog input during a first phase of a clock. A second sample circuit (54) samples the analog input during a second phase of the clock. A comparator (34) compares a reference to the output of the first sample circuit during a non-overlapping time between an end of the first phase and beginning of the second phase and compares the reference to the output of the second sample circuit during a non-overlapping time between an end of the second phase and beginning of the first phase. The first sample circuit (52) couples the sample of the analog input taken by the first sample circuit (52) to the input of the comparator (34) during the non-overlapping time between the end of the first phase and the beginning of the second phase and the second sample circuit (54) couples the sample of the analog input taken by the second sample circuit to the input of the comparator (34) during the non-overlapping time between the end of the second phase and the beginning of the first phase.