发明名称 A DIGITAL ERROR DETECTION ARRANGEMENT
摘要 This invention relates to error detecting arrangements for digital transmission systems. It is particularly applicable to systems in which the line signals are already arranged in or can be converted into a format resulting in what may be termed constant accumulated disparity signals. In a digital transmission system parity information is included so as to cause a toggle in a repeater to take up a particular state immediately following each parity check. This state will only change when an error occurs, or an odd number of errors. When an error has occurred and the toggle has changed its state the new state becomes the normal state and a further change indicates a further error. No special line code is needed and circuitry in the repeater is kept to a minimum. For a binary system it requires an extra digit to be added at reasonable intervals, e.g. after every 100 bits.
申请公布号 AU2560477(A) 申请公布日期 1978.12.07
申请号 AU19770025604 申请日期 1977.05.30
申请人 INTERNATIONAL STANDARD ELECTRIC CORP. 发明人 ANTHONY JESSOP
分类号 H04L1/00;H04L25/49 主分类号 H04L1/00
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