PRIORITY ENCODER CIRCUIT AND METHOD FOR CONTENT ADDRESSABLE MEMORY

摘要

A circuit selects a highest priority signal from a plurality of input signals. The circuit comprises the following components. A plurality of serially coupled input blocks, each of which are coupled to a corresponding one of a plurality of input lines for receiving respective ones of the input signals and providing corresponding output signals. A pre-charging device coupled between a supply voltage terminal and a first one of the serially coupled input blocks. The pre- charging device couples the supply voltage to the first one of the serially coupled input blocks in response to a clock pulse signal transition. An activation device for coupling a last one of the serially coupled input blocks to a ground voltage terminal in response to an activation signal transition. A ground voltage is propagated through the plurality of input blocks up to an input block which reflects a voltage on its input signal that is different from a pre-charge voltage state. The ground voltage terminal is subsequently provided as the only logic low output from said plurality of input blocks representing a highest priority match signal.