发明名称 |
Electronic elements and devices with trench under bond pad feature |
摘要 |
Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material. |
申请公布号 |
US8134241(B2) |
申请公布日期 |
2012.03.13 |
申请号 |
US201113179295 |
申请日期 |
2011.07.08 |
申请人 |
JONES JEFFREY K.;SZYMANOWSKI MARGARET A.;MIERA MICHELE L.;REN XIAOWEI;BURGER WAYNE R.;BENNETT MARK A.;KERR COLIN;FREESCALE SEMICONDUCTOR, INC. |
发明人 |
JONES JEFFREY K.;SZYMANOWSKI MARGARET A.;MIERA MICHELE L.;REN XIAOWEI;BURGER WAYNE R.;BENNETT MARK A.;KERR COLIN |
分类号 |
H01L23/48 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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