发明名称 |
Method and apparatus to reduce footprint of ESD protection within an integrated circuit |
摘要 |
An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground. |
申请公布号 |
US8134813(B2) |
申请公布日期 |
2012.03.13 |
申请号 |
US20090362471 |
申请日期 |
2009.01.29 |
申请人 |
KARP JAMES;LI RICHARD C.;HO FU-HING;FAKHRUDDIN MOHAMMED;XILINX, INC. |
发明人 |
KARP JAMES;LI RICHARD C.;HO FU-HING;FAKHRUDDIN MOHAMMED |
分类号 |
H02H9/00 |
主分类号 |
H02H9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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