发明名称 |
Method and apparatus for hardware-configurable multi-policy coherence protocol |
摘要 |
A processor includes a first level of cache memory and a first set of instructions configured to implement a first cache coherency protocol. The processor also includes a second set of instructions configured to implement a second cache coherency protocol and a cache coherency protocol selector having at least two choice-states. The processor further includes a cache coherency implementer configured to implement the first cache coherency protocol or the second cache coherency with respect to the first level of cache memory based on a selected choice-state of the cache coherency protocol selector.
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申请公布号 |
US8135916(B1) |
申请公布日期 |
2012.03.13 |
申请号 |
US20090416359 |
申请日期 |
2009.04.01 |
申请人 |
O'BLENESS R. FRANK;JAMIL SUJAT;MINER DAVID E.;DELGROSS JOSEPH;HAMEENANTTILA TOM;KEHL JEFFREY;MARVELL INTERNATIONAL LTD. |
发明人 |
O'BLENESS R. FRANK;JAMIL SUJAT;MINER DAVID E.;DELGROSS JOSEPH;HAMEENANTTILA TOM;KEHL JEFFREY |
分类号 |
G06F13/00;G06F13/28 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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地址 |
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