| 摘要 |
A system and a method for reducing interrupt latency is described. The system includes a first interrupt source configured to generate a first interrupt, a second interrupt source configured to generate a second interrupt, and a processor. The processor includes a shadow set that stores data used to service the first interrupt. The processor receives the second interrupt and receives a designation of the shadow set to service the second interrupt. The processor determines, based on a dedicated bit, whether the shadow set is used to service the first interrupt upon receiving the second interrupt.
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