发明名称 |
Method of logic circuit synthesis and design using a dynamic circuit library |
摘要 |
The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design. |
申请公布号 |
US8136061(B2) |
申请公布日期 |
2012.03.13 |
申请号 |
US20080060768 |
申请日期 |
2008.04.01 |
申请人 |
DHONG SANG HOO;HOFSTEE HARM PETER;POSLUSZNY STEPHEN DOUGLAS;SILBERMAN JOEL ABRAHAM;TAKAHASHI OSAMU;WENDEL DIETER F.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DHONG SANG HOO;HOFSTEE HARM PETER;POSLUSZNY STEPHEN DOUGLAS;SILBERMAN JOEL ABRAHAM;TAKAHASHI OSAMU;WENDEL DIETER F. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|