发明名称 Layout structure of power MOS transistor
摘要 The present invention discloses a layout structure of a transistor unit of a power MOS transistor, wherein the layout structure comprises a drain area, a plurality of body areas, a plurality of source areas and a gate area. The plurality of body areas surround the drain area. The plurality of source areas extend from the perimeters of the plurality of body areas in an anisotropic manner. The gate area is disposed between the drain area and the plurality of source areas. The contacts of the drain area, the plurality of body areas and the plurality of source areas are all disposed on the same side of the layout structure.
申请公布号 US8134205(B2) 申请公布日期 2012.03.13
申请号 US20100683053 申请日期 2010.01.06
申请人 TANG MING;CHIAO SHIH-PING;PTEK TECHNOLOGY CO., LTD. 发明人 TANG MING;CHIAO SHIH-PING
分类号 H01L29/66;H01L21/336 主分类号 H01L29/66
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