发明名称 COMMUNICATION SYSTEM
摘要 PURPOSE:To transmit the main signal and the sub-signal simultaneously to utilize the transmission line effectively, by superposing the sub-signal consisting of the digital signal onto the idle time slot of the main signal and by transmitting them. CONSTITUTION:The signal obtained by inputting the sub-signal and the clock signal to AND circuit 4 and the main signal are input to OR circuit 5, and the sub-signal consisting of the digital signal is superposed onto the idle time slot of the main signal, and they are transmitted from transmission unit 6 to receiving unit 8 through transmission line 7. The signal received by receiving unit 8 is input to timing extracting circuit 9 and flip-flop 11. Timing signal components are extracted from the receiving signal by timing extracting circuit 9, and the clock signal for main signal discrimination and the clock for sub-signal discrimination which is the inverted signal of the clock signal above are output to flip-flops 11 and 12.
申请公布号 JPS5631247(A) 申请公布日期 1981.03.30
申请号 JP19790106965 申请日期 1979.08.22
申请人 FUJITSU LTD 发明人 NAGAI YASUO;IFUKURO SADAO
分类号 H04B10/556;H04B10/00;H04B10/524;H04J3/04;H04J3/12 主分类号 H04B10/556
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