| 摘要 |
PURPOSE: An internal clock generation circuit is provided to reduce a current flowing in the internal clock generation circuit using a single buffer among two-stage buffers in a first process. CONSTITUTION: A common buffer(220) outputs an external clock by buffering the external clock when a common enable signal is activated. A first buffer(230) activates a first internal clock by buffering output of the common buffer when a first buffer enable signal is activated. A second buffer(240) activates a second internal clock by buffering the output of the common buffer when a second buffer enable signal is activated. An enable signal generation part controls the second buffer enable signal, the first buffer enable signal, and the common enable signal in response to a plurality of signals. A first driver generates a latch clock by driving the first internal clock. |
