| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a configuration of an ADPLL which can be used for a deskew application, without enlarging the circuit scale of a TDC(Time-to-Digital Converter). <P>SOLUTION: The digital phase lock loop circuit includes a DCO 19, an MDIV 11 which divides an FREF, a PDIV 20 which divides an output FO of the DCO, an NDIV 12 which divides an output FOUT of the PDIV, a TDC 13 which measures a phase difference between an output signal FR of the MDIV and the output FO of the DCO, a TDC 14 which measures a phase difference between an output FD of the NDIV and the FO, an FF 15 which samples the FO with the FR, a CONT 17 which counts the FO during the period between the edges of a pulse of the FR or the FD having a preceeding phaze and the next pulse, a PERR 16 which inputs the outputs of the TDCs 13 and 14 and the FF 15 thereinto and receives an output of a counter to calculate a phase difference between the FR and the FD, and a DFIL 18 which inputs the output of PERR thereinto and supplies a signal that has been filtered to the DCO. <P>COPYRIGHT: (C)2012,JPO&INPIT |
