| 摘要 |
A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor. |
