发明名称 REDUCTION OPERATION DEVICE, A PROCESSOR, AND A COMPUTER SYSTEM
摘要 A reduction operation device detects a non-correspondence of an operation type or a data type in a reduction arithmetic operation of a parallel processing. The reduction operation device is inputted a plurality of the synchronization signals and data, sets each transmission destinations of the plurality of inputted synchronization signals and the plurality of data corresponding to a next stage of a reduction operation and executes the reduction operation. The synchronization unit in the reduction operation device detects the non-correspondence between the operation type or the data type included in an instruction of the reduction operation after the synchronization is established and controls the arithmetic operation of the arithmetic unit.
申请公布号 US2012060019(A1) 申请公布日期 2012.03.08
申请号 US201113166114 申请日期 2011.06.22
申请人 HIRAMOTO SHINYA;AJIMA YUICHIRO;INOUE TOMOHIRO;FUJITSU LIMITED 发明人 HIRAMOTO SHINYA;AJIMA YUICHIRO;INOUE TOMOHIRO
分类号 G06F9/302 主分类号 G06F9/302
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