| 摘要 |
<p>The present invention is provided with a plurality of local bit lines (102) for the simultaneous readout of data, a plurality of voltage change detection circuits (112) provided for each of the local bit lines (102), a global bit line (104), a plurality of column selection circuits (113) for selecting one of the local bit lines (102) and connecting the selected local bit line to the global bit line (104), and a sense amplifier (114) connected to the global bit line (104). The sense amplifier (114) is controlled by a sense amplifier activation signal (105) connected to outputs from the plurality of voltage change detection circuits (112), and thereby utilizes electric discharge from the reading data line not selected to amplify the voltage of the selected reading data line, thus enabling high-speed reading.</p> |
