发明名称 MANUFACTURING METHOD OF HETEROJUNCTION FIELD EFFECT TRANSISTOR
摘要 <P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a heterojunction field effect transistor that suppresses current collapse and reduces gate leakage current. <P>SOLUTION: The manufacturing method of a heterojunction field effect transistor comprises: (a) a step of preparing a nitride semiconductor layer having a laminate on which a channel layer 30, a barrier layer 40, and a cap layer 50 are laminated in this order; (b) a step of forming a cap film 110 which does not include Si on the nitride semiconductor layer; (c) a step of forming an impurity region 60 by selectively implanting an impurity into the nitride semiconductor layer and activating the impurity by heat treatment after the step (b); (d) a step of removing the cap film 110 and forming a source electrode 80 and a drain electrode 90 on the impurity region 60 after the step (c); and (e) a step of forming a gate electrode 100 in the region where at least a part of the nitride semiconductor layer is removed. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012049216(A) 申请公布日期 2012.03.08
申请号 JP20100187985 申请日期 2010.08.25
申请人 MITSUBISHI ELECTRIC CORP 发明人 NANJO TAKUMA;IMAI AKIFUMI;SUZUKI YOSUKE;FUKITA MUNEYOSHI;SHIOZAWA KATSUOMI;ABE YUJI;YAGYU EIJI
分类号 H01L21/338;H01L29/778;H01L29/812 主分类号 H01L21/338
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