发明名称 |
PROCESSOR INDEPENDENT LOOP ENTRY CACHE |
摘要 |
A memory controller is configured to receive read requests from a processor and return memory words from memory. The memory controller comprises an address comparator and a loop entry cache. The address comparator is configured to determine a difference between a previous read request address and a current read request address. The address comparator is also configured to determine whether the difference is positive and less than a certain address difference and, if so, indicate a limited backwards jump. The loop entry cache is configured to store a current memory word for the current read request address when the address comparator indicates a limited backwards jump.
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申请公布号 |
US2012059975(A1) |
申请公布日期 |
2012.03.08 |
申请号 |
US20100874934 |
申请日期 |
2010.09.02 |
申请人 |
LUNADIER FRANCK;SCHUMACHER FREDERIC;ATMEL ROUSSET S.A.S. |
发明人 |
LUNADIER FRANCK;SCHUMACHER FREDERIC |
分类号 |
G06F12/00;G06F12/08 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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