Integrated circuit with gate electrode level including at least four linear-shaped conductive structures of equal length and equal pitch with linear-shaped conductive structure forming one transistor

摘要

A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. The cell also includes a number of interconnect levels formed above the gate electrode level.