发明名称 Stacked integrated circuit packages that include monolithic conductive vias
摘要 Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.
申请公布号 US8129833(B2) 申请公布日期 2012.03.06
申请号 US20090606799 申请日期 2009.10.27
申请人 KANG PIL-KYU;KIM JUNG-HO;LEE JONG-WOOK;CHOI SEUNG-WOO;BAE DAE-LOK;SAMSUNG ELECTRONICS CO., LTD. 发明人 KANG PIL-KYU;KIM JUNG-HO;LEE JONG-WOOK;CHOI SEUNG-WOO;BAE DAE-LOK
分类号 H01L23/02;H01L23/053;H01L23/12;H01L23/48;H01L23/52;H01L27/10;H01L29/40;H01L29/74 主分类号 H01L23/02
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