发明名称 |
Integrated circuit including at least six linear-shaped conductive structive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length |
摘要 |
A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features in the gate electrode level is less than a wavelength of light used in a photolithography process for their fabrication.
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申请公布号 |
US8129757(B2) |
申请公布日期 |
2012.03.06 |
申请号 |
US20090572239 |
申请日期 |
2009.10.01 |
申请人 |
BECKER SCOTT T.;SMAYLING MICHAEL C.;TELA INNOVATIONS, INC. |
发明人 |
BECKER SCOTT T.;SMAYLING MICHAEL C. |
分类号 |
H01L27/10 |
主分类号 |
H01L27/10 |
代理机构 |
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地址 |
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