发明名称 |
Integrated circuit with gate electrode level including at least six linear-shaped conductive structures forming gate electrodes of transisters with at least one pair of linear-shaped conductive structures having offset ends |
摘要 |
A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. The cell also includes a number of interconnect levels formed above the gate electrode level.
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申请公布号 |
US8129754(B2) |
申请公布日期 |
2012.03.06 |
申请号 |
US20090571343 |
申请日期 |
2009.09.30 |
申请人 |
BECKER SCOTT T.;SMAYLING MICHAEL C.;TELA INNOVATIONS, INC. |
发明人 |
BECKER SCOTT T.;SMAYLING MICHAEL C. |
分类号 |
H01L27/10 |
主分类号 |
H01L27/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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