发明名称 |
High speed adder design for a multiply-add based floating point unit |
摘要 |
A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays. |
申请公布号 |
US8131795(B2) |
申请公布日期 |
2012.03.06 |
申请号 |
US20080323257 |
申请日期 |
2008.11.25 |
申请人 |
DHONG SANG HOO;MUELLER SILVIA MELITTA;OH HWA-JOON;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DHONG SANG HOO;MUELLER SILVIA MELITTA;OH HWA-JOON |
分类号 |
G06F7/42;G06F7/38;G06F7/483;G06F7/544 |
主分类号 |
G06F7/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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