| 摘要 |
Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read access is increased by partitioning a memory into a group of sub-blocks, associating a parity block with the sub-blocks, and accessing the sub-blocks to read data as needed. Write speeds may be improved by adding a pending write buffer to a group of memory sub-blocks. Such a buffer may be sized to be equal to the group of memory sub-blocks. The pending write buffer is used to handle collisions for write accesses to the same block, allowing two simultaneous writes to any regular memory block to occur. Additionally, a set-associative memory block may be used to improve write speed.
|
