| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide interconnection resources applied to programmable logic devices for accelerating an operating speed of a programmable logic array integrated circuit device. <P>SOLUTION: A programmable logic integrated circuit (10) has a plurality of programmable logic regions (20) disposed on a device in an array of intersecting rows and columns of the plurality of regions. Interconnection resources (e.g., interconnection conductors or the like) are provided for forming programmable interconnections region to region and/or between the regions. At least some of these interconnection resources are configured in two forms having architecturally similar but significantly different signal transmission speed characteristics. For example, a major or larger portions (200a, 210a, 230a) of the dual-form interconnection resources have what is termed a normal speed, and smaller portions (200b, 210b, 230b) have a significantly faster signal speed. <P>COPYRIGHT: (C)2012,JPO&INPIT |
