发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT, CIRCUIT TESTING SYSTEM, CIRCUIT TESTING UNIT, AND CIRCUIT TEST METHOD
摘要 This invention has an object of providing a semiconductor integrated circuit enabling further reduction of the number of test terminals without depending on a compression/expansion technique alone. The semiconductor integrated circuit of the invention is connected to a terminal group used to exchange test information of a circuit to be tested, and comprises a utilization device which utilizes, when reading a test result, a terminal subgroup of the terminal group, which is not used to transmit information required to read the test result, to receive the test result from the circuit to be tested.
申请公布号 US2012049883(A1) 申请公布日期 2012.03.01
申请号 US201013256583 申请日期 2010.04.09
申请人 INOUE HIROAKI 发明人 INOUE HIROAKI
分类号 G01R31/26 主分类号 G01R31/26
代理机构 代理人
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