发明名称 LEAKAGE CURRENT REDUCING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To reduce a leakage current during operation stop (during standby) of a logical circuit that intermittently operates, and to enable sufficiently supplying a drive current during operation of the logical circuit. <P>SOLUTION: In the leakage current reducing circuit that controls power switches connected between the logic circuit and a power supply in accordance with intermittent operation of the logic circuit, the two power switches are formed so that an nMOS transistor is connected between the logic circuit and a positive power supply potential, and a pMOS transistor is connected between the logic circuit and ground potential, a switch for connecting the gate terminal of the pMOS transistor to the positive power supply potential when the logic circuit stops operation to bring them into a nonconducting state, and connecting the gate potential of the pMOS transistor to the ground potential when the logic circuit operates to bring them into a conducting state is provided, and a voltage converter for setting the gate terminal of the nMOS transistor at ground potential when the logic circuit stops operation to bring them into a nonconducting state, and setting the gate terminal of the nMOS transistor at the positive power supply potential or higher when the logic circuit operates to bring them into a conducting state is provided. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012044696(A) 申请公布日期 2012.03.01
申请号 JP20110225766 申请日期 2011.10.13
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 UGAJIN MAMORU;SUZUKI KENJI
分类号 H03K19/00;H01L21/822;H01L27/04;H03K19/0948 主分类号 H03K19/00
代理机构 代理人
主权项
地址