发明名称 |
PLACEMENT OPTIMIZING METHOD/APPARATUS AND APPARATUS FOR DESIGNING SEMICONDUCTOR DEVICES |
摘要 |
A method of finding the optimal placement of circuit elements is disclosed in which the optimal position of each circuit element is determined from the results of arithmetic operations performed by a processor network (12) where a plurality of processors are interconnected so as to form a neural network, and each processor takes in its own output and the outputs of all other processors to solve a problem. |
申请公布号 |
US5200908(A) |
申请公布日期 |
1993.04.06 |
申请号 |
US19900533540 |
申请日期 |
1990.06.05 |
申请人 |
HITACHI, LTD. |
发明人 |
DATE, HIROSHI;HAYASHI, TERUMINE |
分类号 |
H01L21/82;G06F15/18;G06F17/50;G06F19/00;G06N3/00;G06N3/10;G06Q10/04 |
主分类号 |
H01L21/82 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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