发明名称 Method of manufacturing power semiconductor device
摘要 A mask layer having a plurality of openings is formed on the first layer. A second layer having a second conductivity type different from the first conductivity type is formed on the first layer by introducing impurities using the mask layer. A third layer having the first conductivity type is formed on the second layer by introducing impurities using the mask layer. A trench extending through the second layer and the third layer to the first layer is formed by carrying out etching using an etching mask including at least the mask layer. A gate insulation film covering a sidewall of the trench is formed. A trench gate filling the trench is formed on the gate insulation film.
申请公布号 US8124533(B2) 申请公布日期 2012.02.28
申请号 US20090558999 申请日期 2009.09.14
申请人 NARAZAKI ATSUSHI;MITSUBISHI ELECTRIC CORPORATION 发明人 NARAZAKI ATSUSHI
分类号 H01L21/311 主分类号 H01L21/311
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