发明名称 |
Method for generating a clock signal |
摘要 |
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal. |
申请公布号 |
US8127171(B2) |
申请公布日期 |
2012.02.28 |
申请号 |
US20090568532 |
申请日期 |
2009.09.28 |
申请人 |
JANZEN LEEL S.;ROUND ROCK RESEARCH, LLC |
发明人 |
JANZEN LEEL S. |
分类号 |
G06F1/12;G06F1/04;G11C7/10 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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