发明名称 |
Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor |
摘要 |
Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache. |
申请公布号 |
US8127085(B2) |
申请公布日期 |
2012.02.28 |
申请号 |
US20080317959 |
申请日期 |
2008.12.31 |
申请人 |
RAPPOPORT LIHU;KOREN CHEN;SALA FRANCK;LEMPEL ODED;OUZIEL IDO;KIM ILHYUN;GABOR RON;LIBIS LIOR;PRIBUSH GREGORY;INTEL CORPORATION |
发明人 |
RAPPOPORT LIHU;KOREN CHEN;SALA FRANCK;LEMPEL ODED;OUZIEL IDO;KIM ILHYUN;GABOR RON;LIBIS LIOR;PRIBUSH GREGORY |
分类号 |
G06F12/06 |
主分类号 |
G06F12/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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