发明名称 |
Plasma display having latch failure detecting function |
摘要 |
A test pattern generation circuit outputs a test pattern during a clock phase adjustment period. A flip-flop circuit latches the test pattern at the fall of a shift clock and outputs it as a test pattern. A latch miss detection circuit outputs a latch miss detection signal indicating presence/absence of a latch miss generation according to the test pattern and a delay shift clock. A clock phase controller delays the shift clock according to the latch miss detection signal, thereby outputting a delay shift clock. |
申请公布号 |
US8125410(B2) |
申请公布日期 |
2012.02.28 |
申请号 |
US20040567357 |
申请日期 |
2004.08.04 |
申请人 |
TANAKA KAZUHITO;NIWA AKIO;KASAHARA MITSUHIRO;MASUMORI TADAYUKI;SEIKE MAMORU;PANASONIC CORPORATION |
发明人 |
TANAKA KAZUHITO;NIWA AKIO;KASAHARA MITSUHIRO;MASUMORI TADAYUKI;SEIKE MAMORU |
分类号 |
G09G3/28;G09G3/20;G09G3/288;G09G5/00 |
主分类号 |
G09G3/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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