| 摘要 |
A method for operating a digital logic semiconductor component, wherein: the logic semiconductor component is operated in several operational modes at respective fixed clock cycles depending on environmental temperatures; each operational mode is allocated a respective clock cycle with, in each case, a different clock frequency; each operational mode is allocated a respective temperature-dependent limit value with, in each case, a different limit temperature which when reached causes a change of operational mode to occur; and, when changing to an operational mode with a higher limit temperature, the clock frequency is reduced, and when changing to an operational mode with a lower limit temperature, the clock frequency is increased.
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