发明名称 |
Eliminating silent store invalidation propagation in shared memory cache coherency protocols |
摘要 |
A method and circuit for eliminating silent store invalidation propagation in shared memory cache coherency protocols, and a design structure on which the subject circuit resides are provided. A received data value is compared with a stored cache data value. When the received data value matches the stored cache data value, a first squash signal is generated. A received write address is compared with a reservation address. When the received write address matches the reservation address, a reservation signal is generated and inverted. The first squash signal and the inverted reservation signal are combined to selectively produce a silent store squash signal. The silent store squash signal cancels sending an invalidation signal. |
申请公布号 |
US8127083(B2) |
申请公布日期 |
2012.02.28 |
申请号 |
US20080033088 |
申请日期 |
2008.02.19 |
申请人 |
KUNDINGER CHRISTOPHER J.;LINDBERG NICHOLAS D.;STEC ERIC J.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KUNDINGER CHRISTOPHER J.;LINDBERG NICHOLAS D.;STEC ERIC J. |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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