| 摘要 |
PURPOSE: A duty cycle correcting circuit and a clock generating circuit with the same are provided to adjust a relative delay value of an input clock and an inverted clock of the input clock, thereby correcting a duty cycle of a clock. CONSTITUTION: A delay unit(310) adjusts a relative delay value of an input clock and an inverted clock of the input clock in response to at least one control signal. The delay unit outputs a positive clock and a negative clock. A duty sensor(320) receives the positive clock and the negative clock. The duty sensor generates at least one control signal by sensing a duty cycle ratio. The delay unit comprises a constant delay unit which outputs the constant clock by adjusting a delay value of the input clock. The delay unit outputs a sub clock by adjusting a delay value of an inverted clock of the input clock. |
