| 摘要 |
A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers (163) with gates coupled to a bit line decoder (120) control lead (322), sources/drains coupled to a bit line driver (304), and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode (300) coupled between a bit line and a first bleeder diode controller (314), and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller (314) connects the first bleeder diode (300) to low voltage (305) in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal. |
