| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a transmission circuit and a communication system which can mitigate timing constraint of a control signal distributed for synchronization among a plurality of transmission lanes, and reduce design man-hours. <P>SOLUTION: A transmission circuit comprises: a plurality of lane parts 330-0 to 330-3 which are arranged in parallel, convert supplied parallel data into serial data, and output them; and a clock enabler part 320 which outputs a driving clock synchronized in phase with a reference clock to the plurality of lane parts after progress of a plurality of cycles of the driving clock according to an enable signal CLKEN. Each of the plurality of lane parts 330-0 to 330-3 comprises: frequency dividers 331-0 to 331-3 which divide the driving clock from the clock enabler and generate a frequency division clock and a load signal; and parallel-serial converter 332-0 to 332-3 which convert the parallel data to serial data in synchronous with the frequency division clock and the load signal from the frequency dividers and the driving clock. <P>COPYRIGHT: (C)2012,JPO&INPIT |
