发明名称 ERROR CHECK CIRCUIT AND ERROR CHECK METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide an error check circuit which can confirm validity of data transmission on a small circuit scale. <P>SOLUTION: A parity arithmetic unit 6 generates a parity bit. A CRC error detection unit 7 generates a CRC code by using the parity bit output by the corresponding parity arithmetic unit 6 and performs error detection using the CRC code. A check sum error detection unit 10 generates a check sum for each of communication data and performs error detection using the check sum. A detection circuit 14 detects an error of the communication data based on the error detection result using the check sum and the error detection result using the CRC code. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012039552(A) 申请公布日期 2012.02.23
申请号 JP20100180325 申请日期 2010.08.11
申请人 FUJITSU ADVANCED ENGINEERING LTD 发明人
分类号 H04L1/00 主分类号 H04L1/00
代理机构 代理人
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