| 摘要 |
A computer system having an interconnection apparatus for interconnecting processors, peripherals, and memories, including a bus structure with an extended-bus portion and a non-extended-bus portion, and the extended-bus-compliant devices having a status register. The extended-bus-compliant devices are operable in either extended-bus mode involving both the extended-bus portion and non-extended-bus portion of the bus structure, or non-extended-bus mode involving only the non-extended-bus portion. Upon detecting a transmission error or device-related fault, the contents of the status register are altered so as to render the extended-bus-compliant devices operable in the non-extended-bus mode using only the non-extended-bus portion.
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