| 摘要 |
A clock recovery circuit enables a time for obtaining synchronized state of one pair of gate voltage-controlled oscillator to be shortened in a phase locked loop (PLL). In the clock recovery circuit, data 06 is inputted to a pulse-duration generating circuit 01, generating pulse width less than 1/4 minimum data cycle from H of pulse, L of pulse, or both edges of H and L, thus the pulse is outputted both to a latched-circuit and a synchronous delay circuit 03. The synchronous delay circuit 03 causes a delay time in proportion to data cycle to be generated at both edges of pulse or edge of two pulses, thus the delay time is maintained. An output pulse from a delay circuit 03 is outputted both to a delay circuit 04 and a latched-circuit 05 by way of clock 07 from the pulse synthesis circuit 02. The latch circuit 05 causes the data 06 as an input to be latched by the clock from the pulse synthesis circuit, thus outputting regenerative data 08 in company with the clock 07. <IMAGE> |
