发明名称 Sequential circuit with dynamic pulse width control
摘要 A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.
申请公布号 US8120406(B2) 申请公布日期 2012.02.21
申请号 US20090511608 申请日期 2009.07.29
申请人 IYER ARUN;PATEL SHIBASHISH;JAIN ANIMESH;ATI TECHNOLOGIES ULC 发明人 IYER ARUN;PATEL SHIBASHISH;JAIN ANIMESH
分类号 H03K3/356;H03K3/037 主分类号 H03K3/356
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