| 摘要 |
A delay locked loop circuit comprising a VCDL which outputs a feedback clock by delaying an input clock in accordance with a magnitude of a control voltage, a phase comparator which detects a phase difference between the feedback clock and a reference clock by comparing the feedback clock with the reference clock, and outputs an Up-signal for raising the control voltage and a Down-signal for lowering the control voltage in accordance with the phase difference, a control voltage generation circuit which determines the control voltage in accordance with the Up-signal and the Down-signal, and outputs the control voltage to the VCDL, and a reset circuit which resets the phase comparator based on a logical OR between the reference clock and a first intermediate clock which is a signal obtained by delaying the input clock by the VCDL and is output before the feedback clock. |
