| 摘要 |
A network component comprising a processor configured to implement a method that comprises applying a forward error correction (FEC) algorithm to a plurality of data blocks to generate a plurality of redundancy data, encapsulating an integer number of the data blocks and the redundancy data in an FEC codeword, and transmitting the FEC codeword, wherein the codeword is about evenly aligned with a transmission clock time quanta to have a transmission rate. A method comprising selecting an FEC algorithm that generates a plurality of redundancy data from a plurality of data blocks, selecting an FEC codeword that encapsulates an integer number of the data blocks, and selecting a synchronization pattern to add to the FEC codeword such that an integer number of the FEC codewords are evenly aligned with an integer number of transmission clock time quanta. |
