发明名称 Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates
摘要 In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the combiner unit, the combiner unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an combiner unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the combiner unit.
申请公布号 US8122311(B2) 申请公布日期 2012.02.21
申请号 US201113007278 申请日期 2011.01.14
申请人 SWOBODA GARY L.;TEXAS INSTRUMENTS INCORPORATED 发明人 SWOBODA GARY L.
分类号 G01R31/28 主分类号 G01R31/28
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