发明名称 |
Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits |
摘要 |
A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction. |
申请公布号 |
US8122404(B2) |
申请公布日期 |
2012.02.21 |
申请号 |
US20090388932 |
申请日期 |
2009.02.19 |
申请人 |
SINHA DEBJIT;BHANJI ADIL;DORFMAN BARRY L.;KALAFALA KERIM;VENKATESWARAN NATESAN;VISWESWARIAH CHANDRAMOULI;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
SINHA DEBJIT;BHANJI ADIL;DORFMAN BARRY L.;KALAFALA KERIM;VENKATESWARAN NATESAN;VISWESWARIAH CHANDRAMOULI |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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